Lithographic projection apparatus (lithography tools) can be used, for example, in the manufacture of ICs. When using the various lithography tools, a mask (or reticle) can be used that contains a circuit pattern corresponding to an individual layer of the IC, and this pattern, usually having many designs, can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate, such as a silicon wafer or other wafer comprising a semiconductor surface, that has been coated with a layer of radiation-sensitive material, such as a resist. In general, a single wafer may contain a network of adjacent target portions that can be successively irradiated using a projection system of the tool, one at a time.
One of the goals in IC fabrication is to faithfully reproduce the original IC design on the wafer using the mask. Another goal is to use as much of the wafer area as possible. As the size of an IC is reduced and its feature density increased, however, the critical dimension (CD) of its corresponding mask (or reticle) approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool can be defined as the minimum feature sizes that the exposure tool can repeatedly expose on the wafer. The resolution value of exposure tools often constrains the minimum CD possible for advanced IC designs.
Traditionally, models required for computational lithography which generate imaging parameters for lithography tools are collected inline (empirical) to provide an extensive data-set from one selected (or “golden”) lithography tool until the root mean squared (RMS) error for the imaging parameters are minimized. The corrected mask/reticle derived from the golden lithography tool is utilized for any tool in the fab, or across another fab. Since about the 130 nm process node, the mask/reticle derived using this methodology is progressively unable to be patterned across different tools with high process yield. The same mask/reticle exhibits process yield problems even for the golden lithography tool after some preventative maintenance. ICs manufactured using sub-wavelength lithography are thus subject to high CD variability (reflecting in a large variance (σ)), due to imaging tool differences. This situation can cause either device yield loss or require extensive modification of imaging conditions by each tool and associated modification cost at setup to reduce CD variability.